1. Field of the Invention
The invention relates generally to the field of electrical interconnection of stacked microelectronic assemblies.
More specifically, the invention relates to a stackable device that avoids the use of electrically conductive elements on the external surfaces of a layer containing an integrated circuit die by taking advantage of conventional wire bonding equipment to provide an electrically conductive path that is encapsulated in a potting material so as to define an electrically conductive wire bond “through-via” that is accessible from at least the lower surface of the layer.
2. Description of the Related Art
The ability to fabricate very thin, stackable layers containing one or a plurality of homogeneous or heterogeneous integrated circuit chips is desirable and allows high density, high speed electronic systems to be assembled for use in military, space, security and other applications.
Examples of such layers and modules are disclosed in U.S. Pat. No. 6,706,971; Stackable Microcircuit Layer Formed from a Plastic Encapsulated Micro-Circuit; U.S. Pat. No. 7,768,113, Stackable Tier Structure Comprising Prefabricated High Density Feedthrough, U.S. Pat. No. 7,919,844 Tier Structure With Tier Frame Having Feedthrough Structure, U.S. Pat. No. 7,174,627, Method of Fabricating Known Good Dies from Packages Integrated Circuits; U.S. Pat. No. 6,806,559, Method and Apparatus for Connecting Vertically Stacked Integrated Circuits; U.S. Pat. No. 6,797,537, Method of Making Stackable Layers Containing Encapsulated Integrated Circuit Chips With One or More Overlying Interconnect Layers; U.S. Pat. No. 7,872,339, Vertically Stacked Pre-Packages Integrated Circuit Chips; U.S. Pat. No. 6,784,547, Stackable Layers Containing Encapsulated Integrated Circuit Chips With One or More Overlying Interconnect Layers; U.S. Pat. No. 6,117,704, Stackable Layer Containing Encapsulated Chips; U.S. Pat. No. 6,072,234, Stack of Equal Layer Neo-Chips Containing Encapsulated IC Chips of Different Sizes, and U.S. Pat. No. 5,953,588, Stackable Layers Containing Encapsulated IC Chips.
The stacking and interconnection of very thin microelectronic layers permits high circuit speeds in part because of short lead lengths and related reduced parasitic impedance and electron time-of-flight. These desirable features, combined with a very high number of circuit and layer interconnections, beneficially provide relatively large I/O designs to be implemented in a small volume.
The assignee of the instant application, Irvine Sensors Corporation, has been a leader in developing high density packaging of IC chips, originally for use in focal plane modules, and then for use in a variety of computer functions, such as memory. Generally, stacking of IC chips has emphasized use of identical-area chips, each of which performs the same function. The resulting stack is a rectangular parallelepiped (or cube) having substantially planar outer surfaces. One or more of the outer surfaces may have an access plane or side bus in electrical communication with the IC circuitry of the stacked chips, in order to permit connection to external circuitry.
Irvine Sensors was initially “stacking silicon” by obtaining prefabricated silicon wafers having integrated circuitry defined as individual die thereon from a wafer manufacturer, metalizing an upper surface of the wafer to connect each die's bond pads to an edge that is later formed when the die is diced from the wafer; dicing stackable die from the metalized wafer; stacking the stackable die to form die-stacks, and then forming edge connections on one or more sides of each die stack. Irvine Sensors identified certain challenges in fabricating such die stacks by stacking silicon die, however, for several reasons.
First, it was difficult to buy complete prefabricated wafers, for a number of supply chain-based reasons and the fact the wafer manufacturers do not want to reveal their yield or expose their built-in test structures that could make it easier to reverse engineer their circuitry, because the manufacturers do not usually have an existing sales structure for selling whole wafers and because the manufacturers were concerned about liability issues if the stacked product should come to include a defective die.
Second, it is sometimes difficult to form the edge connections on the die stacks because they must be defined upon within the dicing streets (the inactive die surface area between the individual integrated circuit die on the wafer) that have grown continually narrower as dicing technologies have improved. For example, the typical dicing street may be 6 mils or less and the saw kerf may be about 1.5 mils with poor registration relative to the die. As a result, a die's original metallization may be undesirably exposed to the edge and thereby making it troublesome to form further access plane metallization along that edge without shorting or damaging the die circuitry.
Third, the probability of having a defective die in any one die-stack increases dramatically on the basis of the number of wafers in the wafer stack.
As a result of the foregoing problems associated with silicon bare die stacking, Irvine Sensors developed a technology involved creating “neo-wafers” and then stacking “neo-chips” diced from the neo-wafers.
As disclosed more fully in the foregoing patents, the inventors make a “neo-wafer” by providing a bare IC die (preferably pre-tested or “known good” die); arranging the bare die in a spaced arrangement within a wafer-shaped fixture; and then pouring a potting material such as epoxy onto the bare die within the wafer-shaped fixture. The neo-wafers, after being removed from the fixture, are surface metalized and the potted die are cut from the neo-wafers to provide “neo-chips” of equal area that are suitable for stacking. A significant benefit of neo-wafers and neo-chips is that known good die may be used and different sized and number of die may be incorporated into same sized neo-chips.
None of the above prior art devices or methods provides a device that comprises one or more through vias that permit interconnection from the upper surface of an IC to the lower surface thereof to facilitate stacking of such die. What is needed is a device that combines the above attributes but that can be fabricated using well-defined processes at relatively low cost.